1. Field of the Invention
The present invention relates to a pulse width control system, and more specifically, to a pulse width control system for ensuring that serial data pulses are transmitted with uniform pulse widths.
2. Description of the Prior Art
Recently, many popular electronic devices have begun to use a high speed serial bus for providing communication between the electronic devices and computers. Examples of high speed serial buses include USB (Universal Serial Bus) and IEEE 1394. With each of these two buses, data is transmitted at high speed one bit at a time.
Reffering to FIG. 1. FIG. 1 is a circuit diagram of a prior art differential pair circuit 10 used for transmitting data to a high speed serial bus. Serial data signal DATA is sent across the serial bus and transmitted by the differential pair circuit 10. The differential pair circuit 10 contains a first transistor M1 and a second transistor M2 for respectively producing a positive data signal DataP and a negative data signal DataN. In addition, a bias voltage Vbias is applied to a third transistor M3 for biasing the differential pair circuit 10. The first transistor M1 is controlled by a first control signal CTRL1 and the second transistor M2 is controlled by a second control signal CTRL2. Each of these control signals selectively opens and closes the corresponding transistors according to a value of the serial data signal DATA. The serial data signal DATA can either transmit a logical value of “0”, “1” when in transmit mode, or not transmit any values when in idle mode. The following logic values are given under the assumption that first and second transistors M1 and M2 are PMOS transistors, although any kind of transistors could be used. Please see Table 1 below to see the relationship between values of the serial data signal DATA, the first and second control signals CTRL1 and CTRL2, and the positive and negative data signals DataP and DataN.
TABLE 1MODEDATACTRL1CTRL2DataPDataNTransmit01001Transmit10110Idle—1100
When the serial data signal DATA has a value of “1”, the first control signal CTRL1 closes the first transistor M1 and the second control signal CTRL2 opens the second transistor M2. The exact opposite happens when the serial data signal DATA has a value of “0”. Thus, during transmit mode, the positive data signal DataP is an exact duplicate of the serial data signal DATA, and the negative data signal DataN is the logical opposite. In idle mode, the serial data signal DATA does not transmit any data. During this situation, the first and second control signals CTRL1 and CTRL2 each have a value of “1”. Therefore, the positive and negative data signals DataP and DataN each have a value of “0”.
A differential signal DIFF is calculated by subtracting the negative data signal DataN from the positive data signal DataP. Reffering to FIG. 2. FIG. 2 is a timing diagram of the differential signal DIFF with respect to the serial data signal DATA. As shown in FIG. 2, when the serial data signal DATA is in idle mode, the differential signal DIFF has a value of 0 volts since both the positive and negative data signals DataP and DataN have a value of 0 volts. When the serial data signal DATA is has a value of “1”, the differential signal DIFF has a value of +V volts (V represents a voltage value of logical “1”) since the positive data signal DataP has a value of +V volts and the negative data signal DataN has a value of 0 volts. Finally, when the serial data signal DATA is has a value of “0”, the differential signal DIFF has a value of −V volts since the positive data signal DataP has a value of 0 volts and the negative data signal DataN has a value of V volts. As shown by the sloped lines connecting the +V and −V values of the differential signal DIFF, low slew rates limit the speed at which the differential signal can change values.
Unfortunately, when switching from idle mode to transmit mode, the prior art differential pair circuit 10 has a problem of non-uniform pulse widths. Reffering to FIG. 3. FIG. 3 is a timing diagram showing pulse widths of data signals generated by the differential pair circuit 10. Values of the positive data signal DataP, the negative data signal DataN, and the differential signal DIFF are all shown with respect to time. From time t0 to t1, the serial data signal DATA is in idle mode. Therefore both the positive and negative data signals DataP and DataN and the differential signal DIFF all have a value of 0 volts. At time t1, the serial data signal data switches from idle mode to transmit mode, and the value of the positive data signal DataP begins to rise to +V volts. Because of the slew rate, however, it takes until time t2 to actually reach the value of +V volts. The value of positive data signal DataP continues to have a value of +V volts until time t4. At time t4, the value of the positive data signal DataP gradually begins to change to 0 volts, and by time t5, the value is back at +V volts. Finally, this value of +V volts is kept from time t5 until time t6. As shown from time t1 to t6, when in transmit mode, the negative data signal DataN has exactly the opposite logical value of the positive data signal DataP. Therefore, the differential signal DIFF ranges from a maximum value of +V volts to a minimum value of −V volts.
During transmit mode, the differential signal DIFF repeatedly alternates between pulses with a +V value and pulses with a V value. However, upon careful inspection of FIG. 3, it can be seen that the width of first pulse of the positive data signal DataP is actually larger than any of the other pulses. By comparing first and second pulses of the positive data signal DataP, the difference becomes more apparent. The first pulse lasts from time t2 to time t4, while the second pulse lasts from time t5 to t6. The difference in pulse width between the first and second pulses is noted as ΔT, which is the interval of time from time t2 to time t3. In other words, the interval from time t3 to time t4 is exactly the same interval as from time t5 to time t6.
Since the first pulse of the positive data signal DataP has a larger width, the first pulse of the differential signal DIFF also has a larger width. This anomaly occurs on every first pulse immediately following the switch from idle mode to transmit mode. Thus, every time the differential pair circuit 10 comes out of idle mode and starts receiving data, the first pulse will be wider than all subsequent pulses. This inconsistency in pulse widths leads to potential data corruption due to the change in timing parameters. This means that data could possibly be lost starting from the first pulse in transmit mode.